Note: The job is a remote job and is open to candidates in USA. Team Red Dog is hiring for its client, a Fortune 50 technology leader and next-generation cloud platform company. The Senior Hardware Verification Engineer will drive pre-silicon verification of accelerated networking hardware, developing SystemVerilog/UVM environments, executing comprehensive tests, automating regressions, debugging design issues, and achieving verification closure for complex IP and SoC systems.
Responsibilities
- Develop comprehensive verification plans that address functional requirements, corner cases, and system-level scenarios in collaboration with hardware and software design teams
- Execute verification plans by developing test cases and driving verification closure through functional, code, assertion, and test-plan coverage
- Create and enhance SystemVerilog/UVM verification environments with sequences, constraints, assertions, functional coverage, checkers, scoreboards, and reusable testbench components
- Develop and execute directed, constrained-random, stress, congestion, backpressure, error-injection, and recovery tests
- Debug regressions, perform root-cause analysis, triage defects, and partner with design engineers to resolve critical design, integration, and performance issues
- Build and maintain Python and/or Perl automation supporting test suites, regressions, continuous integration, and continuous development workflows
- Validate networking and hardware functionality across complex IP and SoC-level verification environments
- Track verification progress and coverage metrics to identify gaps and achieve verification closure before milestone releases
- Participate in Agile engineering practices, including code reviews, sprint planning, iterative feature development, and frequent integration
Skills
- 10+ years of hardware design verification experience, with strong hands-on expertise in pre-silicon IP and/or SoC verification and the ability to independently drive verification from test planning through closure
- 10+ years of verification methodology experience, including UVM environments, constrained-random testing, functional coverage, assertions, scoreboards, checkers, regression debugging, and coverage-driven verification
- 10+ years of hands-on SystemVerilog experience developing test cases, sequences, constraints, assertions, functional coverage, and reusable verification components
- Strong scripting and automation skills using Python and/or Perl to support regression execution, test suite maintenance, debugging, and CI/CD verification workflows
- 10+ years of technical engineering experience in hardware design verification, verification methodologies, and SystemVerilog for a Level 5 profile
- Deep hands-on experience with SystemVerilog and UVM in pre-silicon IP and/or SoC verification environments
- Strong understanding of RTL design and hardware verification methodologies
- Experience developing test plans, test cases, sequences, constraints, assertions, functional coverage, and verification infrastructure
- Experience debugging complex hardware issues and driving defects through root-cause analysis and resolution
- Proficiency with Python and/or Perl scripting for verification automation and regression workflows
- Ability to work independently within an established verification environment while collaborating effectively with hardware and software engineering teams
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, Information Technology, or a related engineering discipline required; relevant advanced-degree experience will also be considered
- Ability to complete the full 12-month assignment and support PST working hours, with approximately 2–3 hours of schedule flexibility/overlap
- Candidates with prior Microsoft experience must have at least one continuous year of Microsoft experience
- Fully remote within the U.S.; must be able to support PST working hours, with 2–3 hours of schedule flexibility/overlap acceptable
- All applicants must be authorized to work in the U.S. without the need for sponsorship
- Experience with networking or storage datapaths, SmartNICs, accelerated networking, or related technologies is highly desirable
- Knowledge of hardware protocols such as Ethernet, AXI, AHB, and PCIe is highly desirable
Benefits
- Health insurance (medical, dental, vision, and life)
- Employer-matched 401K plan
- Paid Time Off
- Flexible Paid Holiday Benefit
- Fully remote within the U.S.
Company Overview