Note: The job is a remote job and is open to candidates in USA. Fintal Partners is hiring a Hardware Design Engineer to join a global hardware group building proprietary ASICs for latency-critical trading infrastructure. The role covers ASIC design, RTL development, verification, testing, system integration, and engineering automation in collaboration with hardware, software, research, and trading teams.
Responsibilities
- Work across the entire ASIC lifecycle, from initial specification through integration and rollout
- Write and implement RTL for next-generation ASIC platforms in SystemVerilog
- Weigh in on architecture and design decisions for performance-critical hardware
- Build new capability that keeps pace with changing trading and infrastructure demands
- Partner with hardware, software, and research groups to turn requirements into scalable designs
- Build unit tests and verification environments for RTL designs
- Validate the behavior and performance of hardware blocks
- Root-cause design and integration issues throughout development
- Help shape verification methodology and testing infrastructure
- Make sure designs hold up on reliability, performance, and maintainability
- Write scripts and tooling that make engineering workflows faster
- Push forward automation across design and verification
- Keep improving development methodology and day-to-day engineering practice
Skills
- BS or above in Electrical Engineering, Computer Engineering, Computer Science, or a comparable technical field
- Deep hands-on experience with RTL design and development in SystemVerilog
- Firm grasp of digital design fundamentals
- Working ability in C++
- Track record building and running verification and test strategies
- Exposure to multi-clock-domain designs and clock-domain crossing
- Sound understanding of Ethernet protocols and core networking concepts
- Scripting experience in Python, Bash, or similar
- Sharp debugging and problem-solving instincts
- Comfortable collaborating across different engineering disciplines
- Prior ASIC development experience
- FPGA development background with relevant ASIC design exposure
- Familiarity with PMA (Physical Media Attachment) technologies
- Experience with high-performance networking systems
- Background in low-latency or performance-sensitive system design
- Time spent in trading, market infrastructure, or fintech environments
- Experience building verification frameworks or test automation tooling
- Strong C++ development ability
Company Overview