Note: The job is a remote job and is open to candidates in USA. Qualcomm Technologies, Inc. is dedicated to transforming the industry by developing next-generation computing platforms. The Signal Integrity Architect role involves developing high-performance signal integrity solutions for advanced server applications, collaborating with cross-functional teams, and contributing to the definition and verification of signal integrity for high-speed interconnects.
Responsibilities
- Own SI analysis, simulation, and design closure for CXL 2.0/3.0 interfaces, including channel budget development, , margin analysis and lab methodology support
- Collaborate with SoC, applications engineering, packaging, and system design teams to define and implement system interconnects that meet the unique demands of high-end server environments
- Contribute to SI guidelines development, provide feedback on PCB stack-ups, routing constraints, via structure design, and material selection
- Develop full-topology SI models, simulations, and final designs across assigned interface domains
- Perform SI analysis on 2.5D/3D structures and contribute to the establishment of design guidelines for advanced packaging integration
- Own SI analysis and design guidelines for GPIO/LSIO interfaces such as SPI, I3C, and proprietary paralle interface including signal integrity characterization, termination, and compliance
- Support customer-facing SI collateral development — guidelines, application notes, and simulation models for CXL interfaces
- Develop design automation tools and methodologies. Set technical direction for SI aspects of design within your area of ownership and drive innovating design methodologies
- Prepare and present technical documentation and reports to stakeholders, including engineering teams, senior management, customers, and suppliers
Skills
- Master's degree in Electrical or Computer Engineering, with a specialization in Signal Integrity (SI)
- 8+ years of experience in SI analysis, simulation, and measurement of high-speed digital systems
- Strong knowledge of SI fundamentals, including power distribution networks (PDN), EMIR, transmission line theory, crosstalk, S-parameters, and channel simulations
- Expertise in CXL 2.0/3.0 specifications and/or PCIe Gen5+ SerDes standards, including channel simulation and compliance methodology
- Experience with GPIO, LSIO, and low-speed interface SI characterization and design guidelines
- Familiarity with SerDes standards (PCIe, CXL, USB, Ethernet, etc.)
- Experience owning end-to-end methodologies, encompassing packaging, PCBs, connectors and cabling
- Proficiency with 2D/2.5D/3D EM simulation tools such as ANSYS HFSS/HFSS3DL, Cadence Sigrity, Dassault Systèmes CST, Keysight ADS, and Synopsys' HSPICE
- Hands-on experience creating complex SI models and performing both frequency and time-domain simulations
- Proficiency in Unix/Linux environments and experience with EDA tools through scripting
- Strong knowledge of packaging and PCB technologies, design, and manufacturing processes
- Proven ability to work independently and collaboratively within a cross-functional team environment
- Strong technical documentation skills and excellent written and verbal communication
- Ph.D. in Electrical or Computer Engineering, specializing in SI
- 12+ years of experience in SI analysis, simulation, and measurement of high-speed digital systems
- In-depth understanding of computational electromagnetics and transmission line theory
- Hands-on experience with CXL 2.0/3.0 channel simulation, compliance testing, and debug on server-class platforms
- Hands-on experience with electrical validation and compliance testing using tools like VNAs, oscilloscopes, spectrum analyzers, TDR, probing and fixture design to ≥60GHz
- Familiarity with 2.5D/3D packaging technologies, such as CoWoS, InFo, EMIB, and RDL
- Proficiency in DDR5 and LPDDR5X timing budgets, jitter analysis, and PHY design/link analysis
- Experience with SI simulation for PCIe Gen6+, multi-gigabit serial buses (112Gbps+), UCIE, etc
- Experience with package and PCB design tools such as Cadence Allegro
- Proficiency in scripting with MATLAB, Perl, and Python
- Prior experience contributing to customer-facing SI reference documentation or application notes for server or networking platforms
Benefits
- Competitive annual discretionary bonus program
- Opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus)
- Highly competitive benefits package (designed to support your success at work, at home, and at play)
Company Overview
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