Note: The job is a remote job and is open to candidates in USA. CBL Solutions is seeking an experienced Physical Design Engineer to support block-level ASIC/SoC implementation. The role manages physical design from floorplanning through tape-out, including timing closure, PPA optimization, physical signoff, cross-functional issue resolution, and automation scripting.
Responsibilities
- Execute physical design flow from floorplan, placement, CTS, routing, ECOs through tape-out
- Develop and optimize floorplans, macro placement, utilization, congestion, and routability
- Drive timing closure and optimize PPA (power, performance, area)
- Perform CTS, routing, ECO implementation, and physical design debugging
- Support STA, IR Drop, EM, DFM, and physical verification activities
- Collaborate with STA, DFT, RTL, and signoff teams to resolve implementation issues
- Support tape-out and signoff closure activities
- Develop automation and productivity scripts using TCL, Perl, and/or Python
Skills
- Strong hands-on experience in ASIC/SoC Physical Design
- Synopsys Fusion Compiler experience is required
- Floorplanning & Macro Placement
- Placement Optimization
- Clock Tree Synthesis (CTS)
- Routing
- ECO Implementation
- Timing Closure
- Congestion & Utilization Optimization
- Understanding of LEF/DEF, Liberty, Verilog , and physical design file formats
- Knowledge of IR Drop, EM, DFM, and Physical Verification
- Strong scripting skills in TCL, Perl, and/or Python
- Experience supporting tape-out/signoff activities
- Experience with advanced process nodes
- Full-chip implementation experience
- Experience with signoff tools, DFM, and multiple successful tape-outs
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