Note: The job is a remote job and is open to candidates in USA. TYLsemi builds chiplet infrastructure IP, including I/O, power delivery, and interconnect building blocks for AI and high-performance computing systems. The Package Design Engineer will own IC package design from bump and ball map definition through substrate routing, signal and power integrity closure, and tapeout for high-speed digital and data-center products.
Responsibilities
- Own end-to-end package design in Cadence Allegro Package Designer (APD) for design feasibility studies through tapeout: bump/UBM mapping, ball map planning, substrate stack-up definition, and fan-out/escape routing
- Route and close high-speed signal nets (e.g. Parallel interfaces such as UCIe, LPDDR/DDR; SerDes - interfaces such as PCIe, Ethernet and UFS) using controlled-impedance and length-matching techniques
- Design and optimize power delivery networks (PDN) for IC package, including plane splits, decoupling strategy, and via stitching
- Partner with SI/PI engineering - use SIPI feedback to iterate and harden the package design
- Drive DRC/DFM closure with substrate vendors; manage design review cycles through tapeout
- Collaborate cross-functionally with mechanical/thermal/reliability engineering on warpage, CTE mismatch, and underfill selection for package robustness
- Document design decisions, stack-up specifications, and via schedules for design reuse and knowledge transfer
Skills
- Typically, 5+ years of relevant experience in IC package design
- Bachelor's or Master's degree in Electrical/Mechanical/Electronics Engineering, or related field
- Working knowledge of package-level SI/PI, thermal, and mechanical issues
- Strong analytical and problem-solving skills
- Effective cross-functional communicator, able to work with silicon design, SI/PI, test engineering, mechanical/reliability, and external substrate vendors
- Experience with Cadence SKILL or equivalent tool for design automation
- Experience with 2.5D interposer design using Cadence Innovus/Integrity (or equivalent) for silicon interposer / RDL routing
- Proficiency in Cadence Sigrity/Ansys HFSS/Keysight ADS for package level extraction/analysis of package/interconnect structures
- Proficiency in Ansys IcePack/Cadence Celsius for package thermal simulation
- Experience with advanced packaging, Cu Pillar bump technology, and fine-pitch UBM design
- Working proficiency in Cadence PCB design tools (Allegro X/ PCB Editor / Design Entry HDL) for board-level layout and package-board co-design
- Familiarity with JEDEC package reliability qualification standards and package-level thermal/mechanical simulation
- Proficiency in Cadence Allegro Package Designer (APD) and associated package layout tools (bump/ball map planning, substrate routing, stack-up definition) for flip-chip/wirebond packaging
- Demonstrated ability to close package designs against SIPI (signal integrity/ power integrity) feedback loops — iterating stack-up, routing, and PDN design based on simulation and/or lab correlation results
- Solid fundamentals in high-speed digital signal integrity (impedance control, length matching, via stub effects) and power delivery network design
Benefits
- Remote-friendly work arrangement; US team is Bay Area preferred, but the company hires the best people regardless of location.
Company Overview