STA Lead (Static Timing Analysis Lead)
Location:
Remote
Job Description
We are seeking an experienced
STA Lead
to drive static timing analysis, timing signoff, and timing closure for complex ASIC/SoC designs at block and full-chip levels.
Key Responsibilities
Lead STA methodology, timing signoff, and timing closure activities across block-level and full-chip designs.
Develop and validate SDC constraints and MMMC timing scenarios.
Perform setup/hold analysis, timing optimization, and Timing ECO implementation.
Execute signoff using Synopsys PrimeTime (PT, PT-SI, PBA).
Analyze and resolve timing issues related to signal integrity, crosstalk, noise, and OCV effects.
Apply AOCV, POCV, and statistical timing analysis methodologies.
Review clock architecture, cross-domain timing, and tape-out readiness.
Automate timing analysis and reporting using TCL and Python.
Required Qualifications
Strong experience in STA, timing signoff, and timing closure for ASIC/SoC designs.
Expertise in Synopsys PrimeTime, SDC constraints, and MMMC methodology.
Hands-on experience with SI, crosstalk, noise, OCV, AOCV, and POCV.
Strong understanding of clock design, Timing ECOs, and physical design flows.
Proficiency in TCL and/or Python scripting.
Experience supporting advanced technology nodes and full tape-out cycles is preferred