Note: The job is a remote job and is open to candidates in USA. EnCharge AI develops advanced AI hardware and software systems for edge-to-cloud computing. The company is seeking a Staff Physical Design Engineer to lead block-level and top-level physical implementation of semiconductor chips, optimize timing, power, and area, and guide designs through foundry tapeout.
Responsibilities
- Drive block-level and top-level physical design, including floor-planning, placement, clock tree synthesis (CTS), and routing
- Achieve aggressive timing, power, and area (PPA) targets through advanced timing closure techniques
- Perform power grid verification and manage electromigration and IR drop (EM/IR) analysis and resolution
- Develop and maintain automation scripts (Tcl/Python) to streamline design flows and methodologies
- Collaborate with physical verification and foundry teams to ensure design rule compliance and successful tapeout execution
Skills
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field
- 10–15 years of dedicated experience in physical design
- Strong understanding of EDA implementation flows with extensive experience using Cadence design tools
- Deep understanding of static timing analysis (STA) concepts and advanced timing closure methodologies
- Demonstrated success in top-level and block-level physical design, with hierarchical floorplanning expertise a strong plus
- Proficiency in low-power design techniques, debugging, and EM/IR check resolution/power grid verification
- Strong scripting skills in Tcl or Python for design flow automation
- Solid understanding of advanced process nodes and physical verification requirements associated with routing
- Experience with physical design methodology, flow setup, and advanced flow evaluations
- Prior experience with PDK management or foundry tapeout processes is highly desirable
Company Overview
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