Note: The job is a remote job and is open to candidates in USA. Triple Crown is seeking an experienced ASIC RTL Designer to develop and validate RTL for ASIC designs. The role focuses on RTL design, logic equivalence checking, LINT and CDC checks, static timing analysis, and collaboration with verification and physical design teams.
Responsibilities
- Develop and maintain synthesizable RTL for ASIC designs
- Perform logic equivalence checks to verify design consistency across RTL and gate-level representations
- Run and resolve LINT and clock domain crossing (CDC) checks
- Perform static timing analysis and collaborate with implementation teams to address timing issues
- Work with verification and physical design teams to resolve issues and support design milestones
- Document design specifications, constraints, and changes
Skills
- Hands-on experience designing RTL specifically for ASICs
- Proficiency in Verilog and/or SystemVerilog
- Experience with logic equivalence checking
- Experience running and debugging LINT and CDC checks
- Working knowledge of static timing analysis and timing constraints
- Strong debugging and problem-solving skills
- Experience with LPDDR memory interfaces
- Familiarity with NVMe
- Experience with PCIe Gen 4 and/or Gen 5
Benefits
- Health, Dental and Vision Insurance
- 401k
- Remote work
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