Note: The job is a remote job and is open to candidates in USA. Delos Data is hiring a Senior RTL Design Engineer to design, implement, and deliver high-quality RTL for complex digital systems. The role translates architectural specifications into scalable microarchitectures and production-ready RTL, emphasizing performance, power, and area while collaborating across architecture, verification, and physical design.
Responsibilities
- Design and implement RTL for complex digital subsystems using Verilog/SystemVerilog
- Translate architectural specifications into clean, efficient, and scalable microarchitectures
- Collaborate with architecture, verification, and physical design teams to ensure design correctness and closure
- Develop high-quality, reusable RTL with strong coding standards and documentation
- Perform linting, CDC analysis, and ensure synthesis readiness of designs
- Support integration and debug of RTL in simulation and early silicon environments
- Participate in design reviews and provide technical input on architecture and implementation tradeoffs
- Work with verification teams to ensure comprehensive functional coverage
- Assist in timing closure and support backend teams as needed
- Contribute to continuous improvement of design methodologies, flows, and tools
Skills
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field
- 5+ years of experience in RTL design
- Strong hands-on experience with Verilog/SystemVerilog
- Solid understanding of synchronous digital design and microarchitecture principles
- Experience with simulation and debug tools (e.g., VCS, Questa, Verdi, DVE)
- Familiarity with synthesis, timing, and physical design constraints
- Strong analytical and problem-solving skills
- Clear written and verbal communication skills for cross-functional collaboration
- High attention to detail and ability to deliver high-quality design outcomes
- Ability to work independently and manage tasks to completion, including AI-assisted workflows
- Experience designing high-performance systems (e.g., AI/ML accelerators, networking, or SoCs)
- Familiarity with low-power design techniques (clock gating, power gating)
- Exposure to DFT concepts and design-for-test considerations
- Experience with scripting (Python, Tcl, or similar)
- Experience working in advanced semiconductor process nodes
- Experience using AI coding agents (e.g., Claude Code, Cursor, Copilot) in RTL workflows such a implementation, debug, and timing closure, with the rigor to verify AI-generated output
- Interest in turning design experience into reusable AI agent guidance, such as RTL coding patterns, timing-closure playbooks, or review checklists
Benefits
- Meaningful equity
- 401(k)
- Remote work
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