Note: The job is a remote job and is open to candidates in USA. Mirafra Technologies is seeking an experienced RTL design professional to lead ASIC/SoC block and subsystem development. The role is responsible for micro-architecture, synthesizable Verilog/SystemVerilog RTL, PPA optimization, design signoff, cross-functional collaboration, debugging, and technical leadership.
Responsibilities
- Lead RTL design and micro-architecture development for complex ASIC/SoC blocks and subsystems
- Translate architecture and system requirements into high-quality, synthesizable Verilog/SystemVerilog RTL
- Own block-level design from specification through RTL signoff and tapeout
- Design data paths, control logic, FSMs, pipelines, clock/reset architecture, and high-performance digital logic
- Drive PPA (Power, Performance, Area) optimization and design trade-offs
- Lead RTL Lint, CDC/RDC, synthesis, STA, low-power and connectivity checks
- Work closely with Architecture, Design Verification, Physical Design, DFT, Firmware, and Validation teams
- Debug issues across simulation, synthesis, implementation, and post-silicon bring-up
- Participate in design reviews and establish RTL coding/design best practices
- Mentor junior and senior engineers and provide technical leadership and design ownership
Skills
- 7+ years of hands-on ASIC/SoC RTL design experience
- Strong expertise in Verilog/SystemVerilog and digital design fundamentals
- Proven experience in micro-architecture development and block ownership
- Strong knowledge of AMBA AXI/AHB/APB , clock/reset design, and SoC integration
- Experience with Lint, CDC/RDC, synthesis, STA, and timing closure
- Understanding of low-power design, UPF/CPF, clock gating, and power domains
- Experience with Synopsys, Cadence, or Siemens EDA tools
- Scripting experience in Python, Tcl, Perl, or Shell
- Strong debugging, communication, technical leadership, and cross-functional collaboration skills
Company Overview
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