Note: The job is a remote job and is open to candidates in USA. Meta builds technologies that help people connect, find communities, and grow businesses, including immersive augmented and virtual reality experiences. Meta is seeking a principal-level AI Systems Engineer to define hardware architecture strategies for AI-accelerated computing systems, with a focus on silicon, imaging, camera pipelines, and hardware-software co-design for next-generation wearables, headsets, and spatial computing platforms.
Responsibilities
- Define multi-generation hardware architecture strategy for AI inference and training systems across VR, AR, and wearable device platforms
- Lead system-level architectural exploration and trade-off analysis across compute, memory hierarchy, interconnect fabric, and power delivery for on-device AI workloads
- Architect end-to-end camera and imaging pipelines, including sensor interfaces, ISP integration, and real-time image processing for computer vision and perception applications
- Drive hardware-software co-design initiatives by partnering with silicon engineering, firmware, camera systems, and ML platform teams to optimize end-to-end AI and imaging pipeline performance
- Define architectural requirements for camera subsystems including multi-camera synchronization, depth sensing, and low-latency visual processing for AR/VR applications
- Establish architectural requirements and performance targets for custom AI accelerators, ISPs, SoCs, and supporting subsystems in spatial computing devices
- Develop and maintain system performance models and simulation frameworks to evaluate architectural decisions against real-world AI and imaging workload characteristics
- Provide architectural guidance and technical direction across hardware engineering organizations, aligning imaging and AI roadmaps with product and research priorities
- Identify and resolve system-level bottlenecks in imaging latency, AI inference throughput, and energy efficiency for wearable and headset form factors
- Engage with external silicon partners, camera module vendors, and research institutions to evaluate emerging imaging technologies and incorporate them into long-range architecture plans
- Communicate architectural vision and technical rationale to executive leadership and cross-functional stakeholders through written proposals and design reviews
Skills
- 12+ years of experience in hardware systems architecture, with a focus on AI, ML, imaging systems, or high-performance compute systems
- Deep expertise in camera pipeline architecture, including image signal processing (ISP), sensor integration, and end-to-end imaging system design
- Experience defining SoC or system-level architecture for AI inference or training workloads, including memory subsystem design, compute hierarchy, and interconnect topology
- Experience architecting imaging subsystems for real-time computer vision applications, including multi-camera systems, depth sensing, and visual-inertial odometry
- Experience with hardware-software co-design methodologies for on-device AI and imaging workloads, including familiarity with ML compiler stacks and ISP tuning workflows
- Experience developing system performance models and using simulation or analytical frameworks to evaluate architectural trade-offs at scale
- Track record of driving multi-year hardware architecture roadmaps for imaging and AI systems and influencing silicon strategy across large engineering organizations
- Expertise in computational photography pipelines, HDR processing, and neural ISP architectures
- Experience architecting AI and imaging systems for power- and area-constrained wearable or mobile devices, including VR headsets, AR glasses, or similar spatial computing platforms
- Experience evaluating and integrating emerging memory technologies (e.g., HBM, LPDDR5X, in-memory compute) into AI and imaging system architectures
- Background in collaborating with ML research and camera teams to translate novel imaging algorithms and model architectures into hardware-efficient deployment targets
- Familiarity with custom silicon development flows for imaging and AI accelerators, including architecture-to-RTL handoff, physical design constraints, and post-silicon validation
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