About the Opportunity
Hiring Senior Verification Engineers for its ASIC & Networking team, supporting TeraWave’s first in-house silicon program. The program includes a high-throughput modem and a DSP-intensive digital beamformer, with first tapeout targeted for 2027
This is an opportunity to help build the verification strategy, methodology, and infrastructure from the beginning. Your work may span IP, subsystem, and full SoC verification, with ownership aligned to your experience. Areas include CPU subsystems, high-performance interconnects, security, high-speed peripherals, modem datapaths, DSP and beamforming logic, and mixed-signal interfaces.
The team uses constrained-random simulation, formal verification, and processor-driven SoC testing, while developing AI-assisted tools for testbench generation, regression analysis, and coverage closure.
Wireless, modem, baseband, or DSP experience is welcome but not required.
Strong verification skills and system-level thinking are central to this role, with architects and modeling engineers supporting your ramp-up.
Responsibilities
Own verification planning and execution for complex blocks and subsystems, from test plan development through sign-off.
Translate design specifications into verification strategies, measurable coverage goals, and high-risk test scenarios.
Select and apply appropriate methods, including constrained-random simulation, formal analysis, and directed testing.
Develop and maintain verification environments, reference models, scoreboards, protocol monitors, functional coverage, and assertions.
Debug RTL and system-level issues, working with design and architecture teams to resolve failures.
Drive functional coverage closure, regression health, and verification sign-off readiness.
Build regression and continuous integration infrastructure, with reusable components across IP, subsystem, and SoC levels.
Develop and apply AI-assisted tools for stimulus generation, regression triage, and coverage analysis.
Review testbench architecture and debug approaches, and mentor junior verification engineers.
Required Qualifications
Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field, or at least seven years of equivalent experience.
At least five years of professional experience in ASIC or SoC functional verification.
Hands-on expertise in SystemVerilog and UVM or formal testbench development and maintenance.
Experience with metric-driven verification, including planning, assertions, and functional coverage closure.
Experience verifying complex digital control and datapath logic, including RTL and system-level debugging.
Willingness to relocate near a company site in California or Texas if converted to permanent employment.
Preferred Qualifications
Experience with space-based or wireless communications, modem, baseband, or DSP hardware.
Verification experience with LDPC, forward error correction, framing, or beamforming logic using bit-accurate reference models and fixed-point analysis.
Formal verification experience on production silicon, including connectivity, register maps, arbitration, clock domain crossing, or security properties.
Interconnect or network-on-chip verification experience involving performance, bandwidth, quality of service, and deadlock analysis.
Experience verifying reliability features such as error-correcting codes, redundancy, or fault injection.
Experience developing C-based tests or portable stimulus for SoC verification, CPU boot, and firmware-driven scenarios.
Experience applying AI, machine learning, or LLM tools to verification workflows.