DATAmundi.ai is looking to onboard a high volume of junior-level technical resources to support Technical Dataset Creation (Hardware / Digital Systems).
Resource Profile
- Recent graduates or junior-level hardware / digital design engineers
- Background in digital systems, hardware design, or related technical fields
- Ability to understand and produce technical artefacts and documentation
Location
- Remote – open to candidates from any country
Engagement Details
- Indicative hourly rate: ~USD 20/hour
- Expected scale: 50–100 experts
- The scope may be reduced at a later stage, but a relatively high onboarding volume is currently expected
Project Overview
The goal of the project is to build a dataset of 200 000 images focused on:
- hardware design
- digital system diagrams
Each data record consists of:
- 1 diagram image
- 1 associated technical artifact
The dataset is split 50/50 across the following two variants:
Variant 1
- Diagram image + associated HDL code
- Primary languages:
- Verilog
- SystemVerilog
- Supported standards:
- IEEE 1364
- IEEE 1364-2001 Rev. C
- IEEE 1800-2009
- IEEE 1800-2023
- VHDL is permitted for up to 10% of the Variant 1 volume (optional)
Variant 2
- Diagram image + English technical description accurately explaining the diagram
Diagram Categories (3-way split)
A balanced distribution is required across:
- Circuit diagrams
- Timing diagrams (waveforms)
- State diagrams (finite state machines)
Target distribution must remain within ±3% tolerance per category.
Technical Requirements
- At least 60% gate-level diagrams
- Simple diagrams must not exceed 30% of the dataset
- Both gate-level and block-level diagrams are acceptable within these limits
- Technical coverage includes:
- memory chips
- processors
- digital and logical circuits
- Industry-standard references (e.g. AMBA AXI) may be used to ensure technical realism
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