Responsibilities:
Define, develop and optimize comprehensive verification plans and test strategies for digital/mixed-signal IP blocks, subsystems, and full integrated circuits. Work closely with design teams to understand micro-architecture and functional specifications. Create and maintain detailed test plans, coverage models, and verification environments. Drive coverage closure including functional, code, and assertion-based coverage. Generate technical documentation and drive verification reviews. (30%)
Design and implement complex testbenches using SystemVerilog and UVM methodology. Perform block and chip-level register-transfer level (RTL), gate-level and analog/mixed-signal (AMS) verification. Develop directed test cases, constrained-random verification environments and reusable verification components. Debug complex simulation failures and identify root causes in design or verification environments. Improve verification scalability and portability from project to project by environment enhancement and tools automation. Generate and manage continuous integration, regression testing, scoreboards, monitors, and checkers. (30%)
Report to remote verification & design teams. Mentor junior verification engineers. (20%)
Interface with system, digital hardware, embedded firmware, analog and cross functional teams. (10%)
Drive adoption of advanced verification methodologies, best practices and tool evaluation. (5%)
Technical support to silicon lab evaluation, test, product and application engineers. (5%)
Minimum Qualifications:
8+ years of industry experience in integrated circuit design verification (DV)
B.S. or M.S. in Electrical or Computer Engineering
Strong analytical, synthesis and problem solving skills
In-depth knowledge and experience in digital IC verification for mixed-signal ICs with MCU based hardware systems (ARM, RISC-V, PIC, STM32) with memories, custom digital micro-architecture, interfaces, dedicated hardware peripherals, embedded signal processing, external IPs, and analog peripherals.
Proficiency in SystemVerilog as High-level Verification Language and UVM implementation, Verilog/VHDL, scripting languages (Python, Perl), debugging capabilities, and industry leading EDA verification tools (Synopsys, Cadence, Siemens)
Demonstration of technical leadership
Experience with standard hardware protocols (I2C, I3C, SPI, MIPI)
Independent, self-motivated, rigorous, innovating, team player and able to follow through
Excellent verbal and written communication skills
Desired Qualifications
Knowledge of system-level aspects: signal processing, mixed-signal, digital hardware, embedded firmware, analog, modelling, test and application
Experience with analog block behavioral modelling with SV RNM/Verilog/VHDL
Experience with consumer and/or ITA market circuit developments
8+ years in IC design verification; B.S. or M.S. in Electrical/Computer Engineering; SystemVerilog/UVM; RTL/AMS verification; scripting (Python/Perl); strong leadership and communication.
Key Responsibilities
- define verification
- design testbenches
- mentor engineers
Skills & Tools
SystemVerilog, UVM, Verilog, VHDL, Python, Perl, Synopsys, Cadence, Siemens
Job Details
- Category: Engineering
- Seniority: Senior Level
- Commitment: Full Time
- Workplace: Remote — Hyderabad, Telangana, India
- Languages: English
About Semtech
A global provider of semiconductor and IoT connectivity solutions. — Industry: Information Technology