Tittle : Sr. ASIC/SoC Design verification Engineer
Work Location: Fully remote
Duration: 8 months
Terms: W2 Contract Authorized US Worker - US Citizens
Key Skills:
- Application-Specific Integrated Circuit (ASIC)
- System-on-Chip (SoC)
- SystemVerilog and UVM (Universal Verification Methodology)
Position Summary:
- As a Senior Verification Engineer on the ASIC & Networking team, you support clients’ first in-house silicon program, which comprises a high-throughput modem and a DSP-intensive digital beamformer with first tape out targeted for 2027.
- Verification strategy, methodology, and infrastructure are being defined now, and you help define them.
- The work spans IP, subsystem, and full SoC verification, including CPU subsystems, performance-critical interconnects, security, high-speed peripherals, modem datapath and PHY layers, DSP and beamforming compute, and mixed-signal interfaces.
- You own a subset of this scope aligned to your background.
- The team treats constrained-random simulation, formal methods, and processor-driven SoC testing as equal first-class tools and is building an AI-enabled verification platform that includes LLM-assisted stimulus and testbench generation, automated regression triage and failure clustering, and data-driven coverage closure.
- Because none of this is inherited, the engineers who build these capabilities will own them - and grow with the program as it scales.
- Background in wireless communications, modem, baseband, and DSP verification is welcome but not required.
- Architects and modeling engineers support your ramp, and verification judgment and system-level thinking are weighted above domain background.
Responsibilities:
- Own verification planning and execution for complex blocks and subsystems, from test plan through sign-off.
- Translate design specifications into verification strategies, measurable coverage goals, and early identification of high-risk scenarios.
- Select verification methods for each problem, including constrained-random simulation, formal analysis, and directed testing.
- Develop verification environments, reference models, scoreboards, protocol monitors, coverage components, and assertions.
- Drive functional coverage closure, regression health, and sign-off readiness across simulation and formal results.
- Build verification infrastructure, regression and CI systems, and reuse strategy across IP, subsystem, and SoC levels.
- Apply and build AI-assisted verification capabilities for stimulus generation, regression triage, and coverage analytics.
- Review testbench architecture and debug methodology, and mentor junior engineers in verification methodology.
Required Qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field, or 7+ years equivalent experience.
- Minimum five years of professional experience in ASIC or SoC functional verification.
- Hands-on expertise in SystemVerilog, UVM or formal testbench development and maintenance.
- Experience with metric-driven verification for planning, assertions, and functional coverage closure.
- Experience verifying complex digital control and datapath logic, including RTL and system-level debug.
Preferred Qualifications:
- Background in space-based communications, wireless communications, modem, baseband, or DSP hardware.
- Experience verifying LDPC, FEC, framing, or beamforming logic using bit-accurate reference models and fixed-point analysis.
- Formal verification experience on production silicon, including connectivity, register maps, arbitration, CDC, or security properties.
- Experience with interconnect or NoC verification covering performance, bandwidth, QoS, and deadlock analysis.
- Experience verifying fault tolerance and reliability features such as ECC, redundancy schemes, or fault injection.
- Experience developing C-based or portable stimulus for SoC, CPU boot, and firmware-driven test scenarios.
- Experience applying AI, ML, or LLM tooling to stimulus generation, regression triage, or coverage analysis.
Email your resume to usjobs@mavensoft.com to apply!