Position: SoC Verification Engineer
Location: Remote
Experience: 6 10+ years
Job Overview
We are looking for an experienced SoC/ASIC Verification Engineer with strong hands-on expertise in SystemVerilog and UVM to support verification of complex digital/SoC design blocks.
The ideal candidate must have end-to-end UVM experience building verification environments from scratch, including testbench infrastructure, agents, drivers, monitors, sequences, scoreboards, functional coverage, debugging, and regression execution.
Experience with high-speed protocols such as PCIe, Ethernet, or UCIe is highly preferred, but strong end-to-end UVM expertise is the primary requirement.
Key Responsibilities
Take complete technical ownership of verification for 4 5 complex design blocks within a project.
Develop and maintain UVM-based verification environments from scratch.
Build verification components including:
UVM testbench infrastructure
Agents
Drivers
Monitors
Sequencers
Test sequences
Scoreboards
Functional coverage
Develop and execute both directed and constrained-random tests.
Perform detailed test and regression debugging.
Analyze waveforms and identify root causes of functional failures.
Drive functional and code coverage closure through verification sign-off.
Apply protocol knowledge while verifying complex networking/interconnect designs.
Work with customer engineering teams and internal technical leads.
Integrate block-level verification with customer-owned top-level testbench infrastructure.
Perform regression triage and resolve verification issues using industry-standard simulators.
Required Skills
6 10+ years of hands-on ASIC/SoC verification experience.
Strong expertise in SystemVerilog and UVM.
Demonstrated experience developing UVM testbenches from scratch.
Strong understanding of UVM architecture and verification components.
Hands-on experience with test sequences, agents, scoreboards, monitors, drivers, and functional coverage.
Strong debugging and waveform-analysis experience.
Experience with one or more simulators:
Synopsys VCS
Cadence Xcelium
Mentor Questa
Experience with complex digital designs, ASICs, SoCs, networking silicon, switches, NICs, or high-performance interconnects.
Preferred Protocol Experience
Experience with one or more of the following is a strong plus:
UCIe 2.0
PCIe Gen 4/5/6
Ethernet MAC/PCS/PMA
High-speed interconnect protocols
Ideal Candidate
The ideal candidate is someone who can independently take a complex block and handle the complete verification lifecycle from designing the UVM testbench architecture and developing components/sequences to running regressions, debugging failures, closing coverage, and supporting verification sign-off.