Job Summary
We are seeking a Senior Advanced Packaging Engineer based in Taiwan to support the development, integration, qualification, and manufacturing readiness of advanced CoWoS-based, multi-die chiplet packaging for next- generation AI and high-performance computing products. This individual will serve as the primary local engineering interface with foundry manufacturing, substrate suppliers, and system assembly integration partners to drive
engineering builds, package qualification, process optimization, yield improvement, and successful product bring-up through production ramp.
The ideal candidate is a self-driven engineer with strong technical expertise in advanced packaging, excellent communication skills, and the ability to collaborate effectively with global cross-functional teams while proactively
identifying and resolving technical and manufacturing challenges.
Key Responsibilities
- Drive the planning and execution of test vehicles for advanced packaging technologies to enable process development, material evaluation, design validation, and manufacturing readiness.
- Work closely with foundry manufacturing, substrate suppliers, and system assembly integration partners to monitor technology development, engineering builds, tooling readiness, material availability, process maturity, and yield performance.
- Serve as the primary local technical interface to coordinate package development activities, qualification milestones, and manufacturing execution with external partners in Taiwan.
- Lead technical discussions to resolve package integration, manufacturing, quality, and yield issues while driving timely corrective actions.
- Track engineering build schedules, qualification activities, manufacturing readiness, and technical risks to support overall program execution.
- Interface with cross-functional engineering teams to ensure packaging solutions meet technical requirements, product performance targets, and program schedules.• Support root cause analysis and corrective action activities for build issues, quality excursions, material-related concerns, and manufacturing process challenges.
- Ensure packaging solutions meet design-for-manufacturing (DFM), thermal, mechanical, electrical, and reliability requirements at both the component and system levels.
- Contribute to the development of material specifications, process flows, manufacturing guidelines, and best practices based on engineering learning and qualification results.
- Provide regular technical status update reports, risk assessments, and recommendations to the US-based engineering leadership team and global stakeholders.
Required Experience & Qualifications
- Bachelor's degree in Mechanical Engineering, Electrical Engineering, Chemical Engineering, Materials Science, or a related engineering discipline. Master's degree is a plus.
- 8+ years of hands-on experience in advanced semiconductor packaging, including multi-die integration, CoWoS, silicon interposers, silicon bridge, or other advanced chiplet packaging technologies.
- Proven experience planning, developing, and qualifying engineering test vehicles for package technology development, process optimization, and product enablement.
- Strong understanding of advanced substrate technologies, silicon interposers, die-to-die interconnects, fine-pitch assembly, and multi-chip package integration.
- Experience working directly with foundry manufacturing partners, substrate suppliers, OSATs, and system assembly providers during engineering development and product qualification.
- Familiarity with package and board-level reliability testing, thermal cycling, mechanical stress evaluation, and failure analysis methodologies.
- Working knowledge of DFM, DOE, FMEA, root cause and FA analysis, and process qualification methodologies.
- Strong project coordination and communication skills with the ability to manage multiple technical activities across internal and external engineering teams.
- Ability to build strong local relationships with foundry packaging and system assembly partners in Taiwan, collaborating effectively to drive program execution, meet schedule commitments, and ensure technology readiness for successful product bring-up and manufacturing.
- Fluent in both Mandarin and English, with excellent written and verbal communication skills.
- Highly self-motivated, organized, detail-oriented, and capable of working independently in a fast-paced product development environment.
About Eridu
Eridu is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers to deliver Faster AI. Today’s AI performance is frequently limited by communication bottlenecks. Eridu introduces multiple industry-first innovations across silicon, packaging, software, and systems to deliver an order of magnitude improvement in performance and unlock greater GPU utilization to speed training job completion times and tokens-per-second for more profitable inference. We do this while simultaneously reducing capital and power costs and improving reliability.
The company’s solutions and value proposition have been widely validated by leading hyperscalers.
Eridu has raised over $200M to date including its most recent, oversubscribed Series A round. The company is led by a veteran team of Silicon Valley executives who have delivered multiple billion dollar product lines and led multiple companies to billion dollar exits, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (the world’s leading micro-LED company). The company is in execution mode and has a world-class engineering team with decades of experience in state-of-the-art silicon, packaging, optics, software, and systems. Eridu is working with best-in-class supply chain partners including silicon, packaging and systems.
Visit our website eridu.ai to learn more.
Bachelor's degree in engineering or materials science; 8+ years in advanced semiconductor packaging, including chiplets or CoWoS; experience with test vehicles, qualification, manufacturing partners, reliability, DFM, DOE, FMEA, and bilingual Mandarin-English communication.
Key Responsibilities
- planning test vehicles
- coordinating partners
- resolving issues
Skills & Tools
CoWoS, silicon interposers, silicon bridge, Design for Manufacturing (DFM), Design of Experiments (DOE), Failure Mode and Effects Analysis (FMEA)
Job Details
- Category: Engineering
- Seniority: Senior Level
- Commitment: Full Time
- Workplace: Remote — Taipei, Taipei, Taiwan
- Languages: Chinese, English
About Eridu AI
A Silicon Valley-based hardware startup developing infrastructure solutions for AI data centers. — Industry: Manufacturing