Note: The job is a remote job and is open to candidates in USA. Highbrow Technology Inc is seeking an experienced Senior Physical Design Engineer to support ASIC physical design and implementation. The role focuses on the flow from floorplanning through timing closure and physical signoff, while collaborating with RTL, STA, DFT, verification, and other cross-functional teams.
Responsibilities
- Experience in ASIC/SoC Physical Design and RTL-to-GDSII implementation
- Hands-on experience with floorplanning, placement, CTS, routing, and timing closure
- Experience with industry-standard physical design tools such as Cadence Innovus
- Strong understanding of power planning, power grid design, and physical implementation methodologies
- Experience with Static Timing Analysis (STA) and timing optimization
- Hands-on experience with DRC/LVS, LEC, and physical design signoff
- Experience with clock tree synthesis (CTS) and clock optimization
- Knowledge of IR drop, electromigration (EM), and power integrity is a plus
- Experience with hierarchical physical design is a plus
- Experience with multiple technology nodes and tape-outs is a plus
- Familiarity with low-power design techniques such as power gating, multi-Vt, and voltage islands is a plus
- Scripting/programming experience using Tcl, Perl, Python, or similar languages is a plus
- Experience in physical design flow development, automation, or methodology improvement is a plus
- Ability to work closely with RTL, STA, DFT, verification, and other cross-functional teams
Skills
- • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field
- • Relevant experience in ASIC/SoC Physical Design
- • Strong problem-solving and debugging skills
- • Good understanding of the physical design flow from netlist to GDSII
- • Excellent communication and teamwork skills
Benefits
- Remote work option
- Full-time employment
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