Note: The job is a remote job and is open to candidates in USA. CBL Solutions is seeking a Physical Design Engineer to support cutting-edge GPU and high-performance SoC designs. The role focuses on netlist-to-GDSII execution, physical implementation, timing closure, PPA optimization, and resolving advanced-node design issues for TSMC 2nm and 3nm technologies.
Responsibilities
- Own Netlist-to-GDSII for high-speed, low-power SOC
- Floor planning, Placement, CTS, Routing, Timing closure
- Drive PPA optimization - Power, Performance, Area for 2nm/3nm
- Handle advanced nodes issues: IR Drop, EM, Crosstalk etc
- Hands on experience on tools - Synopsys Fusion Compiler, Innovus, Primetime, Calibre
Skills
- Hands-on experience in TSMC 3nm/2nm at SOC for cutting-edge GPU / High-Performance designs
- Hands on experience on tools - Synopsys Fusion Compiler, Innovus, Primetime, Calibre
- Innovus, 2nm, 3nm, 4nm, 5nm
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