Note: The job is a remote job and is open to candidates in USA. Positron AI builds next-generation AI inference accelerators for low-latency, high-throughput large language model inference. The Senior ASIC Physical Design Engineer will contribute to the physical implementation of AI accelerators from floorplanning through tapeout, drive timing and quality-of-result closure, develop implementation methodologies, execute industry-standard design flows, and collaborate with cross-functional engineering teams.
Responsibilities
- Support floorplanning, macro placement, and power planning across Positron's AI accelerator designs
- Drive clock tree synthesis, place and route, and routing optimization through to timing closure on assigned blocks
- Contribute to signal integrity, IR/EM closure, ECO implementation, and metal fill to deliver signoff-quality results
- Support tapeout signoff for physical implementation deliverables
- Contribute to methodology for power grids, power/ground tiles, and bump planning
- Assist in building congestion analysis and wire estimation approaches to support early floorplan decisions
- Support partitioning and hierarchical implementation strategies for complex, multi-block designs, under guidance from senior/principal leads
- Execute Innovus-based implementation flows for assigned blocks
- Apply hands-on expertise across Innovus, ICC2, Tempus, PrimeTime, Voltus, RedHawk, and Calibre
- Drive closure across timing, power, area, congestion, DRC, LVS, EM, IR, and yield for owned blocks
- Partner closely with backend design services to align on implementation strategy and execution
- Participate in implementation quality reviews
- Apply AI-enabled techniques for automated QoR analysis, congestion prediction, routing prediction, and floorplan optimization
Skills
- 5–8 years of experience in physical design, spanning floorplanning through tapeout
- Experience contributing to one or more advanced-node tapeouts
- Strong proficiency in Innovus and/or ICC2 implementation flows
- Solid working knowledge of physical implementation, including floorplanning, clock tree synthesis, timing, and power closure
- Experience supporting signoff across timing, power, and related quality metrics
- This position is open to candidates currently authorized to work in the U.S
- Experience with AI accelerator design
- Familiarity with large SRAM arrays
- Experience with SerDes and LPDDR interfaces
- Exposure to chiplet architectures and 2.5D advanced packaging
Benefits
- Fully company-paid medical, dental, and vision insurance for you and your dependents
- Company-paid life and disability coverage, with voluntary options to add more
- Supplemental hospital, critical illness, and accident coverage available
- Unlimited paid time off, so you can truly unplug and recharge
- 13 paid company holidays
- Remote-first culture with a company-provided computer and home office setup
- Competitive salary and equity
- 401(k) with company matching, eligible from day one
Company Overview
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