Position: DV IP Design Verification Engineer Location: Remote
Employment Type: Contract
Job Summary
We are looking for an experienced Design Verification Engineer with strong expertise in IP/Block-level verification to support verification of complex digital IPs. The ideal candidate will have hands-on experience developing SystemVerilog/UVM-based verification environments, creating verification plans and testcases, debugging RTL and testbench issues, and driving functional/code coverage to closure.
The engineer will work closely with RTL and SoC teams to develop reusable verification components and ensure high-quality IP-level verification.
Key Responsibilities
Develop and enhance SystemVerilog/UVM-based testbenches, including agents, drivers, monitors, scoreboards, sequences, and assertions.
Develop and execute detailed verification plans, testcases, and coverage models.
Create and execute both directed and constrained-random tests for IP/block-level verification.
Integrate and configure UVCs/VIPs and develop reusable verification components.
Drive functional coverage and code coverage closure and manage verification regressions.
Verify RTL functionality of IP blocks, including FSMs, DAC control logic, pattern memory/controller modules, and related digital logic.
Perform detailed debugging of RTL, protocol, testbench, and simulation issues.
Develop and maintain RAL (Register Abstraction Layer) models and perform RAL-based register verification.
Validate register access, prediction, mirroring, reset behavior, and coverage.
Develop and debug SystemVerilog assertions (SVA) for functional and protocol verification.
Support GLS/debug and low-power verification activities as required.
Collaborate closely with RTL designers, SoC teams, and other verification engineers to resolve issues and deliver reusable verification collateral.
Required Qualifications
Strong hands-on experience with SystemVerilog and UVM.
Solid experience in IP/Block-level Design Verification.
Strong experience developing and maintaining UVM testbenches.
Experience with UVM agents, sequences, scoreboards, monitors, drivers, assertions, and constrained-random verification.
Hands-on experience with RAL/Register verification.
Strong understanding of digital design, RTL, FSMs, and verification methodologies.
Experience with functional coverage, code coverage, regression management, and coverage closure.
Experience with protocol verification and assertions/SVA.
Experience integrating or working with VIPs/UVCs.
Strong RTL and simulation debugging skills.
Familiarity with low-power verification and GLS debug is preferred.
Strong analytical and problem-solving skills.