Design Verification IP Engineer

Design Verification IP Engineer Location: Remote Client Microsoft/ HCL Need W2 Only USC & GC Job Description: Responsible for IP/Block-level verification through developing reusable verification environments, executing verification plans, debugging, and coverage closure. Key Responsibilities Develop and enhance UVM-based testbenches, agents, scoreboards, and assertions. Develop and execute comprehensive verification plans, testcases, and coverage models. Create and execute directed and constrained-random test scenarios for IP verification. Integrate and configure UVCs/VIPs and drive functional and code coverage closure. Verify RTL functionality of IP blocks including FSMs, DAC control logic, and pattern memory/controller modules. Debug RTL, protocol, and verification environment issues. RAL Modeling and Verification Collaborate with RTL and SoC teams to deliver high-quality, reusable verification collateral. Skill Requirements Strong SystemVerilog and UVM programming experience. Hands-on expertise in IP/Block-level verification and testbench development. Strong understanding of digital design fundamentals, FSM architectures, and RTL verification. Hands-on experience in RAL modeling and RAL-based register verification, including register access, prediction, mirroring, and coverage. Experience with protocol verification, assertions, coverage analysis, and regression management. 6.Familiarity with low-power verification concepts and GLS debug. 7.Strong analytical, debugging, and problem-solving skills. Thanks & Regards, Vinay Rama Sesha rama@g3softinc.com +1 732-807-0584 +91 9059962085 Whats App Number